The use of ESD protection circuitry for protecting an integrated circuit (IC) device from damage caused by the discharge of static electricity and/or other transient pulses (e.g., load dump) through the device is well known. An ESD event, which may include any large voltage and/or current transient pulse, may not necessarily cause immediate (i.e., catastrophic) failure of the device, but may damage only a portion of the device and/or cause a latent defect that can significantly shorten the operating life or negatively impact the reliability of the device.
Certain applications, such as, for example, electronic fuse (eFuse) programming, involve the application of a relatively high-energy (e.g., voltage and/or current) signal from a suitable power supply source to an IC. In the case of eFuse programming, a voltage greater than that allowed for a specified gate oxide reliability of an IC is typically applied to one or more pins (e.g., eFuse programming pin) of the IC. The voltage applied to the IC pin is routed through a selected eFuse to be programmed, thereby causing the resistance of the eFuse to change. This programming voltage is only applied to the IC pin for a relatively short period of time and then the pin is tied to ground in a subsequent read operation for verifying the state programmed into the eFuse.
IC pins typically include standard ESD clamping circuits for protecting circuitry coupled to the IC pins from becoming damaged as a result of an ESD event. While the use of standard ESD clamping circuits may be acceptable in many eFuse programming applications when the programming voltage is applied to the IC for a very short period of time (e.g., less than one second), it is often difficult to adhere to this short programming time requirement with any consistency. When a high-energy signal, such as, for example, an eFuse programming signal, is applied to the pin of a packaged IC device, as may be required in a post-packaging eFuse programming operation, circuitry coupled to the IC pin can be damaged, often as a result of a compromised gate oxide in the ESD protection circuit, which is undesirable.
Accordingly, there exists a need for an improved ESD protection circuit suitable for use in a high-voltage environment that does not suffer from one or more of the problems exhibited by conventional ESD protection circuits.